1. Field of the Invention
The present invention relates generally to a semiconductor process, and more specifically to a semiconductor process, which performs a plasma process without oxygen to densify an oxide layer in a dual spacer.
2. Description of the Prior Art
For decades, chip manufacturers have obtained faster metal-oxide-semiconductor (MOS) transistors by making them smaller. As the semiconductor processes advance to the very deep sub micron dimensions such as 65-nm node or below, increasing the driving current for MOS transistors has become a critical issue. In order to improve device performances, crystal strain technology has been developed. Crystal strain technology is becoming more and more attractive as a mean for getting better performances in the field of MOS transistor fabrication. Putting a strain on a semiconductor crystal alters the speed at which charges move through that crystal. Strains make MOS transistors work better by enabling electrical charges, such as electrons, to pass more easily through the silicon lattice of the gate channel.
For the known arts, attempts have been made to use a strained silicon layer, which had been grown epitaxially on a silicon substrate with an epitaxial layer such as a silicon germanium (SiGe) layer disposed in between. In this type of MOS transistor, a biaxial tensile strain occurs in the epitaxial layer due to the silicon germanium which has a larger lattice constant than silicon, and, as a result, the band structure alters, and the carrier mobility increases. This enhances the speed performances of the MOS transistors. In another way, silicon carbide may be used to form an epitaxial layer for N-MOS transistors.
The steps of forming the epitaxial layer in the substrate beside the gate structure may include: a single-layer spacer is formed beside a gate structure, which may include a gate dielectric layer, a gate electrode layer and a spacer, in order to automatically etch the substrate and form at least a recess in the substrate beside the spacer. Then, an epitaxial layer is formed in the recess. The spacer is removed. Subsequent semiconductor processes, such as a source/region implantation process, are performed on the substrate and the gate structure.
However, some drawbacks occur when the single-layer spacer is applied. For instance, due to over-etching, the substrate below the single-layer spacer, which may have a lightly-doped source/drain region formed therein, will be damaged when the spacer is removed. Besides, a first spacer may be formed on the substrate beside the gate structure to form a lightly-doped source/drain region before the single-layer spacer is formed. The first spacer will be damaged when the single-layer spacer is removed after the epitaxial layer is formed, due to the material similarity of the single-layer spacer and the first spacer, thereby affecting the electrical performances of MOS transistors.